1. Field of the Invention
The present invention relates to an on-die termination control circuit and a method of generating an on-die termination control signal, and more particularly to, an on-die termination control circuit and a method of generating an on-die termination control signal to differentiate an impedance of the on-die termination circuit during a write mode and a read mode.
2. Discussion of Related Art
Since an operation of a semiconductor device gets high-speed, a swing width of interface between semiconductor devices has been shortened. It is for minimizing a delay time taken by transferring a signal. However, the narrower the swing width is, the more an influence from an external noise is increased, and also a reflection of a signal according to an impedance mismatching gets more critical in an interface terminal. The impedance mismatching is caused by an external noise, a variation of a power source voltage, a variation of operating temperature, or a variation of a manufacturing process. When the impedance mismatching occurs, it is difficult to transfer a data in a high speed and it causes to distort an output data outputted from an output terminal of the semiconductor device. Therefore, when a semiconductor device of a receiver receives the distorted output data into an input terminal, it can frequently cause those problems such as setup/hold time failure or mismatch of an input level.
Accordingly, a semiconductor device requiring high speed operation employs an impedance matching circuit, which is referred as to an on-chip termination or an on-die termination, near around a pad of an integration circuit chip.
A part of semiconductor memory devices, such as a DDR Double Data Rate SDRAM among semiconductor devices, has employed a termination circuit which is embodied with a resistor with values of resistance.
FIG. 1 is a schematic diagram illustrating a conventional termination circuit.
Referring to FIG. 1, a termination circuit is generally connected to an input/output pad PD100 and performs a role as a resistor during turn-on state, by including a pull-up transistor P100 and a pull-down transistor N100. Here, the pull-up transistor P100 is connected between a power source voltage VDDQ terminal and the input/output pad PD100, and the pull-down transistor N100 is connected between a ground terminal and the input/output pad PD100. Here, if the termination circuit is designed to perform a termination operation of 60Ω, each of the pull-up transistor P100 and the pull-down transistor N100 is available to get 120Ω for values of an on-resistance. The pull-up transistor P100 is operated by a pull-up control signal PB and the pull-down transistor N100 is operated by a pull-down control signal NB, to output data through the input/output pad PD100.
On the other hand, when the data is inputted to the input/output pad PD100, the data is inputted into an internal circuit through a buffer B100. In this case, the conventional termination circuit only gets a value of an on-resistance by setting, which makes various termination operations according to variations of receiving conditions more difficult. Especially, in case of GDDRIII, because a required impedance differentiates during a data output and during a data input, when the termination is pre-set with a default value, it isn't possible to perform an adaptable termination operation.
As a result, in order to adaptively perform an optimized termination operation, it has been necessary to improve an on-die termination technique which can change the impedance according to an operating mode, in a high speed semiconductor device.